Matthew Hagerty

FPGA, VHDL, VDP, 9918A, electronics, PCB

TMS-9918A Family Differences

The TMS-9918A family has several variations that differ primarily in the video output format (composite or component) and frame rate (60Hz or 50Hz). There are also some differences in the clock signals generated by the VDPs, which can include the CPU-Clock and/or GROM-Clock.

The 9118/9128/9129 VDPs are the successors of the 9918A/9928A/9929A VDPs. These newer chips have improved memory addressing circuitry which allows the interface of either eight TMS4116 (2k) DRAMs, or two TMS4416 (8K) DRAMs.

VDP Output Frequency GROMCLK CPUCLK
9918A Composite 60Hz NTSC Yes Yes
9928A Component 60Hz NTSC Yes No
9929A Component 50Hz PAL Yes No
9118 Composite 60Hz NTSC No Yes
9128 Component 60Hz NTSC No Yes
9129 Component 50Hz PAL No Yes

The only variations in the pin-outs between all the devices are pins 35 to 38.

   _________
 =|1   U  40|=          9918A   9928A/29A  9118   9128/29 F18A
 =|2      39|=         ======== ========= ======= ======= ====
 =|3      38|= ....... CPUCLK   R-Y       CPUCLK  R-Y     HI-Z / CPUCLK
 =|4      37|= ....... GROMCLK  GROMCLK   NC      CPUCLK  GROMCLK / CPUCLK
 =|5      36|= ....... COMVID   Y         COMVID  Y       NC
 =|6      35|= ....... EXTVDP   B-Y       EXTVDP  B-Y     NC

F18A User Jumpers

The F18A has a set of four “USER” jumpers to set various options. Two of the jumpers control the GROMCLK and CPUCLK output pins to allow the F18A to be compatible with all 9918A family ICs. The other two set sprite and virtual-scan-line power-on defaults.

All user inputs have pull-ups in the FPGA, so a jumper in place will pull to ground.

Jumper Description On Off
1 Sprite max default 32 4
2 Scan lines No Yes
3 CPUCLK pin P38 P37
4 CPUCLK en HI-Z CPUCLK

Jumper 3 and 4 quick guide:

VDP USR3 USR4 Notes
TI-99/4A on on The 99/4A does not use the CPUCLK, but this is NOT the default of the 9918A.
9928/29 on on CPUCLK on pin38 disabled so it does not cram 3.5MHz into the R-Y circuit.
9918A/9118 on off CPUCLK output, GROMCLK output (pin37 is not connected on the 9118).
9128/29 off on CPUCLK on pin37 enabled, CPUCLK output on pin38 disabled.
not used off off CPUCLK output on both pin37 and pin38.

F18A Pin Out

Any pins marked “NC” (no-connect) are installed for physical support only. Pins that are missing a use symbol (= > < - #) are physically not installed on the F18A. The function of each pin is identical to the original 9918A, except the ~RESET pin does NOT support the SYNC functionality of the 9918A.

       _________
  NC -|1   U  40|- NC
  NC -|2      39|- NC
      |3      38|> CPUCLK (3.58MHz)
      |4      37|> GROMCLK (447.4KHz)
      |5      36|- NC
      |6      35|- NC
      |7      34|< ~RESET
      |8      33|# VCC 5V
      |9      32|
      |10     31|
      |11     30|
 GND #|12     29|
MODE >|13     28|
~CSW >|14     27|
~CSR >|15     26|
~INT <|16     25|
 CD7 =|17     24|= CD0
 CD6 =|18     23|= CD1
 CD5 =|19     22|= CD2
 CD4 =|20     21|= CD3
      `---------'
     
MODE in host mode select.
~CSW in host write strobe.
~CSR in host read strobe.
~INT out VDP frame interrupt.
CD7..0 in/out host to VDP data bus, CD7 is the LSbit (TI bit-numbering from this era).
~RESET in host system reset.
GROMCLK out GROM Clock.
CPUCLK out CPU Clock.

MK2 Pin Out

The MK2 has all pins physically installed and electrically connected. The pins necessary to communicate with the host system (MODE1, MODE2, ~CSW, ~CSR, ~INT, CD7..0, and ~RESET) are all fixed-direction (CD7..0 is direction controlled), level-shifted and 5V tolerant. All other pins are either dedicated purpose or direct I/O to the FPGA and are 3.3V ONLY.

           _________
AUDIO IN >|1   U  40|< ADC IN
 GPIO 8P =|2      39|> DAC OUT
 GPIO 9N =|3      38|> CPUCLK (3.58MHz)
GPIO 10P =|4      37|> GROMCLK (447.4KHz)
GPIO 11N =|5      36|= GPIO 12P
    VREF <|6      35|= GPIO 13N
     TMS >|7      34|< ~RESET
     TDI >|8      33|# VCC 5V
     TCK >|9      32|= GPIO 0P
     TDO <|10     31|= GPIO 1N
   MODE2 >|11     30|= GPIO 2P
     GND #|12     29|= GPIO 3N
   MODE1 >|13     28|= GPIO 4P
    ~CSW >|14     27|= GPIO 5N
    ~CSR >|15     26|= GPIO 6P
    ~INT <|16     25|= GPIO 7N
     CD7 =|17     24|= CD0
     CD6 =|18     23|= CD1
     CD5 =|19     22|= CD2
     CD4 =|20     21|= CD3
          `---------'
     
MODE1 in host mode select.
~CSW in host write strobe.
~CSR in host read strobe.
~INT out VDP frame interrupt.
CD7..0 in/out host to VDP data bus, CD7 is the LSbit (TI bit-numbering from this era).
~RESET in host system reset.
GROMCLK out GROM Clock.
CPUCLK out CPU Clock.
MODE2 in provides 9938 host interface compatibility.
AUDIO IN in accepts a line-level 1Vp-p audio signal that is sampled and digitized via the ADC.
ADC IN in direct input to the ADC, no filter or buffer. Requires a solder jumper to connect.
DAC OUT out direct output from the DAC, no filter. Requires a solder jumper to connect.
VREF out 3.3V reference for the JTAG interface.
TMS, TCK, TDI, TDO in/out JTAG interface to the FPGA.
GPIOxx in/out unbuffered general purpose I/O, will be high-impedance with the MK2 firmware. The I/Os are routed as positive/negative pairs to the FPGA.

Tested System Compatibility

The F18A has been installed in the following systems:

  • TI-99/4A Home Computer
  • ColecoVison Game Console (1)
  • ColecoVision ADAM Computer (1)
  • Toshiba HX-10 MSX1 Computer
  • Toshiba Pasopia-IQ MSX1 Computer
  • JVC Victor HC-7 MSX1 Computer
  • Yamaha CX5M MSX1 Computer
  • SpectraVideo 328 Computer (1)
  • Tomy Tutor (1)
  • SEGA SG-1000 (2)
  • SEGA SC-1000II (replaced a TMS9118 VDP)
  • Telegames Personal Arcade
  • Powertran Cortex
  • Memotech 500 and 512 (2)

Note 1: These systems are known to have the original VDP soldered directly to the system circuit board, and will require desoldering the original VDP and a socket installed.

Note 2: The placement and orientation of the original VDP in these systems prevents the system case from being closed when the F18A is installed.